Static Timing Analysis for Nanometer Designs pdf epub mobi txt 電子書下載2025

簡體網頁||繁體網頁

☆☆☆☆☆

出版者:

作者:Bhasker, J.

出品人:

頁數:594

译者:

出版時間:2009-6

價格:$ 236.17

裝幀:

isbn號碼:9780387938196

叢書系列:

圖書標籤:

IC
STA
FPGA
本門內功
Static Timing Analysis
STA
Nanometer Designs
VLSI
Digital Design
Timing Verification
IC Design
Semiconductor
Electronics
Low Power
Design Automation

下載連結在頁面底部

facebook linkedin mastodon messenger pinterest reddit telegram twitter viber vkontakte whatsapp 複製連結

想要找書就要到小美書屋

book.quotespace.org

立刻按 ctrl+D收藏本頁

你會得到大驚喜!!

具體描述

The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts. The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology. This book addresses CMOS logic gates, cell library, timing arcs, waveform slew, cell capacitance, timing modeling, interconnect parasitics and coupling, pre- and post-layout interconnect modeling, delay calculation, specification of timing constraints for analysis of internal paths as well as IO interfaces. Advanced modeling and analysis concepts such as controlled current source timing and noise models for nanometer technologies, power modeling including active and leakage power, crosstalk timing and crosstalk glitch calculation, verification of half-cycle and multi-cycle paths, false paths, synchronous interfaces are also covered.