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喜歡 SystemVerilog for Verification 的讀者還喜歡

不會吧，連這書都有？ 好想把它讀懂……

@Quietstream要offer

讀這本書太費勁瞭，英文讀不懂，中文更讀不懂。把asic-world.com上systemverilog的例子全做一遍，結閤著讀這部書會好一點，一點個人體會。

不會吧，連這書都有？ 好想把它讀懂……

讀這本書太費勁瞭，英文讀不懂，中文更讀不懂。把asic-world.com上systemverilog的例子全做一遍，結閤著讀這部書會好一點，一點個人體會。

To read this book, you should have basic knowledge of Verilog. There are many examples in this book, very easy to understand. It's an introduction book for SystemVerilog Verification. If you want learn the language in depth, go IEEE1800 or VMM. You should...  

the best book of introducing verifcation using SV. It is worth taking a careful look. And you should run all the codes by yourself with VCS/NC/modelsim  

正在读，先记录一下感受。 翻译的基本上还可以。就我读过的专业书籍来说，算是平均之上吧。 能看得出来翻译的人是业内人士，而且对书中的例子大概也进行了调试，否则不会出现改动原书的代码的状况。 在第八章我已经发现了至少两个地方对原书代码的改动。很不幸的是，都改错了...  

anyone who can thoroughly understand this book can become the expert of sv verification.  

To read this book, you should have basic knowledge of Verilog. There are many examples in this book, very easy to understand. It's an introduction book for SystemVerilog Verification. If you want learn the language in depth, go IEEE1800 or VMM. You should...