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《國外電子與通信教材係列•數字集成電路:電路、係統與設計(第2版)(英文版)》分三部分：基本單元、電路設計和係統設計。在對MOS器件和連綫的特性做瞭簡要介紹之後，深入分析瞭反相器，並逐步將這些知識延伸到組閤邏輯電路、時序邏輯電路、控製器、運算電路及存儲器這些復雜數字電路與係統的設計中。《國外電子與通信教材係列•數字集成電路:電路、係統與設計(第2版)(英文版)》以0.25微米CMOS工藝的實際電路為例，討論瞭深亞微米器件效應、電路最優化、互連綫建模和優化、信號完整性、時序分析、時鍾分配、高性能和低功耗設計、設計驗證、芯片測試和可測性設計等主題，著重探討瞭深亞微米數字集成電路設計麵臨的挑戰和啓示。《國外電子與通信教材係列•數字集成電路:電路、係統與設計(第2版)(英文版)》內容已根據作者和中文版譯者整理的勘誤錶進行瞭更正。

Part 1 The Fabrics
Chapter 1 Introduction
1.1 A Historical Perspective
1.2 Issues in Digital Integrated Circuit Design
1.3 Quality Metrics of a Digital Design
1.3.1 Cost of an Integrated Circuit
1.3.2 Functionality and Robustness
1.3.3 Performance
1.3.4 Power and Energy Consumption
1.4 Summary
1.5 To Probe Further
Reference Books
References
Chapter 2 The Manufacturing Process
2.1 Introduction
2.2 Manufacturing CMOS Integrated Circuits
2.2.1 The Silicon Wafer
2.2.2 Photolithography
2.2.3 Some Recurring Process Steps
2.2.4 Simplified CMOS Process Flow
2.3 Design Rules—The Contract between Designer and Process Engineer
2.4 Packaging Integrated Circuits
2.4.1 Package Materials
2.4.2 Interconnect Levels
2.4.3 Thermal Considerations in Packaging
2.5 Perspective—Trends in Process Technology
2.5.1 Short—Term Developments
2.5.2 In the Longer Term
2.6 Summary
2.7 To Probe Further
References
Design Methodology Insert A IC LAYOUT
A.1 To Probe Further
References
Chapter 3 The Devices
3.1 Introduction
3.2 The Diode
3.2.1 A First Glance at the Diode—The Depletion Region
3.2.2 Static Behavior
3.2.3 Dynamic， or Transient， Behavior
3.2.4 The Actual Diode—Secondary Effects
3.2.5 The SPICE Diode Model
3.3 The MOS（FET） Transistor
3.3.1 A First Glance at the Device
3.3.2 The MOS Transistor under Static Conditions
3.3.3 The Actual MOS Transistor—Some Secondary Effects
3.3.4 SPICE Models for the MOS Transistor
3.4 A Word on Process Variations
3.5 Perspective—Technology Scaling
3.6 Summary
3.7 To Probe Further
References
Design Methodology Insert B Circuit Simulation
References
Chapter 4 The Wire
4.1 Introduction
4.2 A First Glance
4.3 Interconnect Parameters—Capacitance， Resistance，and Inductance
4.3.1 Capacitance
4.3.2 Resistance
4.3.3 Inductance
4.4 Electrical Wire Models
4.4.1 The Ideal Wire
4.4.2 The Lumped Model
4.4.3 The Lumped RC Model
4.4.4 The Distributed rc Line
4.4.5 The Transmission Line
4.5 SPICE Wire Models
4.5.1 Distributed rc Lines in SPICE
4.5.2 Transmission Line Models in SPICE
4.5.3 Perspective： A Look into the Future
4.6 Summary
4.7 To Probe Further
References
Part 2 A Circuit Perspective
Chapter 5 The CMOS Inverter
5.1 Introduction
5.2 The Static CMOS Inverter—An Intuitive Perspective
5.3 Evaluating the Robustness of the CMOS Inverter：The Static Behavior
5.3.1 Switching Threshold
5.3.2 Noise Margins
5.3.3 Robustness Revisited
5.4 Performance of CMOS Inverter： The Dynamic Behavior
5.4.1 Computing the Capacitances
5.4.2 Propagation Delay： First—Order Analysis
5.4.3 Propagation Delay from a Design Perspective
5.5 Power， Energy， and Energy Delay
5.5.1 Dynamic Power Consumption
5.5.2 Static Consumption
5.5.3 Putting It All Together
5.5.4 Analyzing Power Consumption Using SPICE
5.6 Perspective： Technology Scaling and its Impact on the Inverter Metrics
5.7 Summary
5.8 To Probe Further
References
Chapter 6 Designing Combinational Logic Gates in CMOS
6.1 Introduction
6.2 Static CMOS Design
6.2.1 Complementary CMOS
6.2.2 Ratioed Logic
6.2.3 Pass—Transistor Logic
6.3 Dynamic CMOS Design
6.3.1 Dynamic Logic： Basic Principles
6.3.2 Speed and Power Dissipation of Dynamic Logic
6.3.3 Signal Integrity Issues in Dynamic Design
6.3.4 Cascading Dynamic Gates
6.4 Perspectives
6.4.1 How to Choose a Logic Style？
6.4.2 Designing Logic for Reduced Supply Voltages
6.5 Summary
6.6 To Probe Further
References
Design Methodology Insert C How to Simulate Complex Logic Circuits
C.1 Representing Digital Data as a Continuous Entity
C.2 Representing Data as a Discrete Entity
C.3 Using Higher—Level Data Models
References
Design Methodology Insert D Layout Techniques for Complex Gates
Chapter 7 Designing Sequential Logic Circuits
7.1 Introduction
7.1.1 Timing Metrics for Sequential Circuits
7.1.2 Classification of Memory Elements
7.2 Static Latches and Registers
7.2.1 The Bistability Principle
7.2.2 Multiplexer—Based Latches
7.2.3 Master—Slave Edge—Triggered Register
7.2.4 Low—Voltage Static Latches
7.2.5 Static SR Flip—Flops Writing Data by Pure Force
7.3 Dynamic Latches and Registers
7.3.1 Dynamic Transmission—Gate Edge—triggered Registers
7.3.2 C2MOS—A Clock—Skew Insensitive Approach
7.3.3 True Single—Phase Clocked Register （TSPCR）
7.4 Alternative Register Styles*
7.4.1 Pulse Registers
7.4.2 Sense—Amplifier—Based Registers
7.5 Pipelining： An Approach to Optimize Sequential Circuits
7.5.1 Latch—versus Register—Based Pipelines
7.5.2 NORA—CMOS—A Logic Style for Pipelined Structures
7.6 Nonbistable Sequential Circuits
7.6.1 The Schmitt Trigger
7.6.2 Monostable Sequential Circuits
7.6.3 Astable Circuits
7.7 Perspective： Choosing a Clocking Strategy
7.8 Summary
7.9 To Probe Further
References
……
Part 3 A System Perspective
Chapter 8 Implementation Strategies for Digital ICS
Design Methodology Insert E Characterizing Logic and Sequential Cells
Design Methodology Insert F Design Synthesis
Chapter 9 Coping with Interconnect
Chapter 10 Timing Issues in Digital Circuits
Design Methodology Insert G Design Verification
Chapter 11 Designing Arithmetic Building Blocks
Chapter 12 Designing Memory and Array Structures
Design Methodology Insert H Validation and Test of Manufactured Circuits
Problem Solutions
Index
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